As a conventional wiring forming technique using a dual damascene method, a technique to form an altered layer by applying surface treatment to a region that becomes a wiring trench pattern of a hard mask formed on an interlayer insulating film on a semiconductor substrate and to subsequently form a via hole in the interlayer insulating film by etching the altered layer in the hard mask and the interlayer insulating film using a resist pattern formed on the hard mask as a mask, has been proposed. In this technique, a wiring trench communicated with the via hole is formed in the interlayer insulating film by etching the interlayer insulating film using, as a mask, a hard mask in which the wiring trench pattern is formed by further selectively removing the altered layer. This technique, for example, is disclosed in JP-A-2006-108336.
Here, according to the method described in JP-A-2006-108336, since a resist pattern for forming a via hole is formed on a flat hard mask having an altered layer before the wiring trench pattern is formed, it is possible to accurately form a resist pattern for forming a via hole.
However, according to the method described in JP-A-2006-108336, since a rim of an opening of the via hole in the interlayer insulating film is likely to be removed by etching when forming a wiring trench in the interlayer insulating film, a diameter of the opening of the via hole is expanded (a slope descending toward the via hole is formed on a bottom of the wiring trench). Therefore, the via and the wiring are deformed and a possibility to cause deterioration of electric characteristics arises.